The present invention lies in the field of phase detectors for phase centering. More particularly, the present invention relates to phase detectors for phase centering in a clock regeneration device. The invention also relates to such a clock regeneration device.
Such devices are used to detect the phase difference between a data signal and a clock signal and to produce a control signal, which is representative of the ascertained phase difference. The control signal is then passed to the oscillator device, which produces the clock signal in order to initiate correction in the oscillator device, so that the ascertained phase difference can be corrected.
In U.S. Pat. No. 5,027,085, a phase detector operating in the aforementioned manner is described. In the phase detector, the incoming data are sampled at a clock rate, which corresponds to the clock rate of the incoming data. However, the conventional phase detector is not suitable for use in a clock regeneration device, in which the incoming data are sampled at a clock rate, which corresponds to substantially half the clock rate of the incoming data. Sampling at substantially half the clock rate is customary for transmitting data at a high clock rate at the speed limit of the electrical circuits.
It is accordingly an object of the present invention to provide a phase detector device and a clock regeneration device that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that allows phase centering, when incoming data are sampled at a clock rate which is lower than, in particular substantially half the size of, the clock rate of the incoming data.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a phase detector including a data line transmitting a data at least at a high clock rate, a first clock line for transmitting first clock signals and a second clock line for transmitting second clock signals, a first weighting device, a second weighting device and a third weighting device, a first flip-flop having a first input connected to the data line, a second input connected to the first clock line and an output. A second flip-flop having a first input connected to the output of the first flip-flop, a second input connected to the second clock line and an output, a third flip-flop having a first input connected to the output of the second flip-flop are also provided.
A second input connected to the first clock line and an output, a first XOR gate having a first input connected to the data line, a second input connected to the output of the first flip-flop and an output connected to the first weighting device, a second XOR gate having a first input connected to the output of the first flip-flop and to the first input of the second flip-flop, a second input connected to the output of the second flip-flop and to the first input of the third flip-flop and an output connected to the second weighting device are also provided.
A third XOR gate having a first input connected to the output of the second flip-flop and to the first input of the third flip-flop, a second input connected to the output of the third flip-flop and an output connected to the third weighting device, a fourth flip-flop having a first input connected to the data line, a second input connected to the second clock line and an output, a fifth flip-flop having a first input connected to the output of the fourth flip-flop, a second input connected to the first clock line and an output, a sixth flip-flop having a first input connected to the output of the fifth flip-flop and a second input connected to the second clock line, and correction devices for producing a correction signal are also provided. The first and second clock signals have clock rates corresponding to substantially half the high clock rate, and the first clock signals have a phase shifted by 180xc2x0 with respect to a phase of the second clock signals.
In accordance with another feature of the invention, the correction devices include a further XOR gate having a first input connected to the output of the first flip-flop and a second input connected to the output of the fourth flip-flop, a first AND gate having a first input connected to an output of the further XOR gate, a second input connected to the first clock line and a further input connected to the output of the second flip-flop.
A second AND gate having a first input connected to the output of the further XOR gate and a second input connected to the first clock line, and a fourth, a fifth and a sixth weighting device, the fourth weighting device having a first input of connected to the first clock line, the fifth weighting device having a first input connected to an output of the first AND gate, and the sixth weighting device having a first input connected to an output of the second AND gate are also provided. The correction signal is produced from the output signals of the fourth, fifth and sixth weighting devices. This provides a combination of logic chips, which permits integration of the phase detector in integrated circuits using customary technology.
In accordance with another feature of the invention, there is provided a clock regeneration device including a data line transmitting data at least at a high clock rate, a first clock line for transmitting first clock signals and a second clock line for transmitting second clock signals, a phase detector, an oscillator, and an integrator connected to the phase detector and connected to the oscillator. The oscillator produces the first and second clock signals.
The first and second clock signals have clock rates corresponding to substantially half the high clock rate, and the first clock signals have a phase shifted by 180xc2x0 with respect to a phase of the second clock signals.
In accordance with another feature of the invention, the phase detector feeds the correction signal to the integrator.
In accordance with another feature of the invention, a control signal for the oscillator is produced from the correction signal and from the respective output signals from the first, second and third weighting devices.
In accordance with another feature of the invention, there is provided a clock regeneration device including a frequency detector for frequency centering. The frequency detector is connected to the first and second clock lines and the integrator such that the frequency detector can transmit a frequency detector signal to the integrator. The integrator includes switching devices for producing a control signal from the frequency detector signal, the correction signal and the output signals of the first, second and third weighting devices. In this manner, it is possible to perform frequency centering in addition to phase centering. This is particularly advantageous with the high tolerances of customary semiconductor technologies.
The fundamental advantage, which the present invention achieves over the prior art is that an opportunity is provided for using phase centering at substantially half the clock rate. Accordingly, the phase centering can also be used for data, which are transmitted at high clock rates at the speed limit of electrical circuits.
Other features which are considered as characteristic for the present invention are set forth in the appended claims.
Although the present invention is illustrated and described herein as embodied in a phase detector and a clock regeneration device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the present invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the present invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.